Analysis Delta-sigma modulation

fig. 1: block diagram , waveforms sigma delta adc.



fig. 1a: effect of clocking impulses

shown below block diagram illustrated in fig. 1 waveforms @ points designated numbers 1 5 input of 0.2 volts on left , 0.4 volts on right.

in practical applications summing interval large compared impulse duration , signals significant fraction of full scale variable separating interval small compared summing interval. nyquist–shannon sampling theorem requires 2 samples render varying input signal. samples appropriate criterion 2 successive Σ counts taken in 2 successive summing intervals. summing interval, must accommodate large count in order achieve adequate precision, inevitably long converter can render relatively low frequencies. hence convenient , fair represent input voltage (1) constant on few impulses.

consider first closed feedback loop consisting of analogue adder/subtracter, integrator, threshold crossing detector , impulse generator.

on left 1 input , short interval constant @ 0.2 v. stream of delta impulses generated @ each threshold crossing shown @ 2 , difference between 1 , 2 shown @ 3. difference integrated produce waveform 4. threshold detector generates pulse 5 starts waveform 4 crosses threshold , sustained until waveform 4 falls below threshold. within loop 5 triggers impulse generator produce fixed strength impulse.

on right input 0.4 v , sum during impulse −0.6 v opposed −0.8 v on left. negative slope during impulse lower on right on left.

also sum 0.4 v on right during interval opposed 0.2 v on left. positive slope outside impulse higher on right on left.

the resultant effect integral (4) crosses threshold more on right on left. full analysis show in fact interval between threshold crossings on right half on left. frequency of impulses doubled. hence count increments @ twice speed on right on left consistent input voltage being doubled.the overall effect of negative feedback loop maintain running integral of impulse train equal within 1 impulse running integral of input analogue signal. frequency of impulse train proportional bandwidth limited amplitude of input signal.bandwidth limitation occurs because nyquist–shannon sampling theorem requires 2 impulses per period define highest frequency passed.

construction of waveforms illustrated @ (4) aided concepts associated dirac delta function in impulses of same strength produce same step when integrated, definition. (4) constructed using intermediate step (6) in each integrated impulse represented step of assigned strength decays 0 @ rate determined input voltage. effect of finite duration of impulse constructed in (4) drawing line base of impulse step @ 0 volts intersect decay line (6) @ full duration of impulse.

now consider circuit outside loop. summing interval prefixed time , @ expiry count strobed buffer , counter reset. necessary ratio between impulse interval , summing interval equal maximum (full scale) count. possible impulse duration , summing interval defined same clock suitable arrangement of logic , counters. has advantage neither interval has defined absolute precision ratio important. achieve overall accuracy necessary amplitude of impulse accurately defined. stated, fig. 1 simplified block diagram of delta-sigma adc in various functional elements have been separated out individual treatment , tries independent of particular implementation. many particular implementations seek define impulse duration , summing interval same clock discussed above in such way start of impulse delayed until next occurrence of appropriate clock pulse boundary. effect of delay illustrated in fig. 1a sequence of impulses occur @ nominal 2.5 clock intervals, firstly impulses generated threshold crossed discussed , secondly impulses delayed clock. effect of delay firstly ramp continues until onset of impulse, secondly impulse produces fixed amplitude step integral retains excess acquired during impulse delay , ramp restarts higher point , on same locus free running integral. effect that, example, undelayed impulses occur @ clock points 0, 2.5, 5, 7.5, 10, etc. , clocked impulses occur @ 0, 3, 5, 8, 10, etc. maximum error can occur due clocking marginally less 1 count. although sigma-delta converter implemented using common clock define impulse duration , summing interval not absolutely necessary , implementation in durations independently defined avoids 1 source of noise, noise generated waiting next common clock boundary. noise primary consideration overrides need absolute amplitude accuracy; e.g., in bandwidth limited signal transmission, separately defined intervals may implemented.