Practical Implementation Delta-sigma modulation

fig. 1b: circuit diagram



fig. 1c: adc waveforms

a circuit diagram practical implementation illustrated, fig 1b , associated waveforms fig. 1c. circuit diagram illustration purposes, details of particular manufacturers implementations available particular manufacturer. scrap view of alternative front end shown in fig. 1b has advantage voltage @ switch terminals relatively constant , close 0.0 v. current generated through r −vref constant @ −vref/r less noise radiated adjacent parts of circuit. preferred front end in practice but, in order show impulse voltage pulse consistent previous discussion, front end given here, electrical equivalent, used.

the waveforms shown in fig 1c unusually complex because intended illustrate loop behaviour under extreme conditions,vin saturated on @ full scale, 1.0v, , saturated off @ zero. intermediate state indicated,vin @ 0.4v, , usual operating condition between 0 , 1.0v similar operation of illustrative block diagram, fig 1.

from top of fig 1c waveforms, labelled on circuit diagram, are:-

the clock.

(a) vin. shown varying 0.4 v 1.0 v , 0 volts show effect on feedback loop.

(b) impulse waveform. discovered how acquires form traverse feedback loop.

(c) current capacitor, ic, linear sum of impulse voltage upon r , vin upon r. show sum voltage product r × ic plotted. input impedance of amplifier regarded high current drawn input neglected.the capacitor connected between negative input terminal of amplifier , output terminal. connection provides negative feedback path around amplifier. input voltage change equal output voltage change divided amplifier gain. high amplifier gain change in input voltage can neglected , input voltage held close voltage on positive input terminal in case held @ 0v. because voltage @ input terminal 0v voltage across r vin current capacitor input voltage divided resistance of r.

(d) negated integral of ic. negation standard op. amp. implementation of integrator , comes because current capacitor @ amplifier input current out of capacitor @ amplifier output , voltage integral of current divided capacitance of c.

(e) comparator output. comparator high gain amplifier plus input terminal connected reference 0.0 v. whenever negative input terminal taken negative respect positive terminal of amplifier output saturates positive , conversely negative saturation positive input. output saturates positive whenever integral (d) goes below 0 v reference level , remains there until (d) goes positive respect reference level.

(f) impulse timer d type positive edge triggered flip flop. input information applied @ d transferred q on occurrence of positive edge of clock pulse. when comparator output (e) positive q goes positive or remains positive @ next positive clock edge. similarly, when (e) negative q goes negative @ next positive clock edge. q controls electronic switch generate current impulse integrator. examination of waveform (e) during initial period illustrated, when vin 0.4 v, shows (e) crossing threshold before trigger edge (positive edge of clock pulse) there appreciable delay before impulse starts. after start of impulse there further delay while (e) climbs past threshold. during time comparator output remains high goes low before next trigger edge. @ next trigger edge impulse timer goes low follow comparator. clock determines duration of impulse. next impulse threshold crossed before trigger edge , comparator briefly positive. vin (a) goes full scale, +vref, shortly before end of next impulse. remainder of impulse capacitor current (c) goes 0 , hence integrator slope briefly goes zero. following impulse full scale positive current flowing (c) , integrator sinks @ maximum rate , crosses threshold before next trigger edge. @ edge impulse starts , vin current matched reference current net capacitor current (c) zero. integration has 0 slope , remains @ negative value had @ start of impulse. has effect impulse current remains switched on because q stuck positive because comparator stuck positive @ every trigger edge. consistent contiguous, butting impulses required @ full scale input.

eventually vin (a) goes 0 means current sum (c) goes negative , integral ramps up. shortly thereafter crosses threshold , in turn followed q, switching impulse current off. capacitor current (c) 0 , integral slope zero, remaining constant @ value had acquired @ end of impulse.

(g) countstream generated gating negated clock q produce waveform. thereafter summing interval, sigma count , buffered count produced using appropriate counters , registers. vin waveform approximated passing countstream (g) low pass filter, suffers defect discussed in context of fig. 1a. 1 possibility reducing error halve feedback pulse length half clock period , double amplitude halving impulse defining resistor producing impulse of same strength 1 never butts onto adjacent impulses. there threshold crossing every impulse. in arrangement monostable flip flop triggered comparator @ threshold crossing closely follow threshold crossings , eliminate 1 source of error, both in adc , sigma delta modulator.